Cryptographic Accelerators on the UltraSPARC T2 with the Solaris Cryptographic Framework

As the both the requirement and demand for secure systems increases, so to will the ubiquitousness of cryptography. The most secure cryptographic schemes often involve complicated algorithms and are by no means cheap to implement on standard hardware, and it is this that has led to the development of cryptographic hardware accelerators. Optimizing software to take advantage of these hardware devices is a problem akin to that of effective parallelization and this project aims to determine how these accelerators perform and under what conditions their use is cost-effective. Through the development of code designed to exercise the particular accelerators existing on the Solaris UltraSPARC T2 via the Solaris Cryptographic Framework (SCF) the system’s performance under a variety of different conditions was assessed. A suggestion for the possible design of a benchmark exclusively for hardware accelerated cryptography is also given. The results indicate that substantial performance gains can be had with proper use of the accelerators. Due to the way in which the framework handles cryptographic requests, worrying about explicitly parallelizing the code to make use of more than one of the accelerators is unnecessary beyond 8 threads, yielding a minimal to negligible performance improvement. Benchmarking these types of hardware with general code looks to be difficult, due to the range of differing accelerator types, the algorithms they support and how they are accessed. Accelerators of this kind have huge potential when used correctly with cryptographically heavy services, freeing up the CPU and achieving near wire-speed cryptography for almost zerocost.